1. Field of the Invention
The present invention generally relates to the manufacturing in monolithic form of MOS transistors. More specifically, the present invention relates to the manufacturing of transistors of small dimensions.
2. Discussion of the Related Art
FIGS. 1A and 1B are cross-section views illustrating different steps of the forming of the contacts of a MOS transistor according to a known method.
As illustrated in FIG. 1A, the transistor is formed in an active region of a semiconductor layer 1 on an insulator 2 (SOI), insulator 2 resting on a support 3. Active region 1 is delimited by an insulation periphery 4. Source and drain regions 5 are formed on either side of an insulated gate 7 provided with lateral insulating spacers 9. The entire transistor is embedded in an interlevel insulator. Typically, the interlevel insulator is formed of two successive insulating layers of different natures, a lower layer 11 and an upper level 13 having a planar upper surface.
At the steps illustrated in FIG. 1B, insulating layers 11 and 13 are opened at two selected locations to partially expose source/drain regions 5. The openings thus formed are then filled with a conductive material, typically metallic, such as tungsten, aluminum, copper, or an alloy of one or several of these metals. Vias 15 are thus formed. A contact with gate G is also simultaneously formed.
A disadvantage of such a method lies in the need to provide a lateral guard between the walls of gate 7 and contacts 15. This guard is necessary to avoid a short-circuit between gate 7 and a source/drain region 5 in case of a misalignment of the mask of definition of vias 15.
Since transistors are used as base elements to form a great number of components (resistors, diodes, switches) or circuits (memories, image sensors . . . ), it is desirable to decrease their dimensions.